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HA5024
Data Sheet February 8, 2006 FN3550.6
Quad 125MHz Video Current Feedback Amplifier with Disable
The HA5024 is a quad version of the popular Intersil HA5020. It features wide bandwidth and high slew rate, and is optimized for video applications and gains between 1 and 10. It is a current feedback amplifier and thus yields less bandwidth degradation at high closed loop gains than voltage feedback amplifiers. The low differential gain and phase, 0.1dB gain flatness, and ability to drive two back terminated 75 cables, make this amplifier ideal for demanding video applications. The HA5024 also features a disable function that significantly reduces supply current while forcing the output to a true high impedance state. This functionality allows 2:1 and 4:1 video multiplexers to be implemented with a single IC. The current feedback design allows the user to take advantage of the amplifier's bandwidth dependency on the feedback resistor. By reducing RF , the bandwidth can be increased to compensate for decreases at higher closed loop gains or heavy output loads.
Features
* Quad Version of HA-5020 * Individual Output Enable/Disable * Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800V * Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz * Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/s * Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% * Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees * Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA * ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V * Guaranteed Specifications at 5V Supplies * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Video Multiplexers; Video Switching and Routing * Video Gain Block * Video Distribution Amplifier/RGB Amplifier
Ordering Information
PART NUMBER HA5024IP HA5024IPZ (Note) HA5024IB HA5024IBZ (Note) PART MARKING HA5024IP HA5024IPZ HA5024IB HA5024IBZ TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld PDIP* (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) PKG. DWG. # E20.3 E20.3 M20.3 M20.3
* Flash A/D Driver * Current to Voltage Converter * Medical Imaging * Radar and Imaging Systems
Pinout
HA5024 (PDIP, SOIC) TOP VIEW
OUT1 -IN1 +IN1 1 2 3 4 5 6 7 8 9 + + 20 OUT4
HA5024IBZ96 HA5024IBZ (See Note) HA5024EVAL
M20.3 20 Ld SOIC Tape and Reel (Pb-free)
-
+
-
19 -IN4 18 +IN4 17 DIS4 16 NC 15 V14 DIS3
High Speed Op Amp DIP Evaluation Board
DIS1 NC V+ DIS2 +IN2 -IN2
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
-
+
-
13 +IN3 12 -IN3 11 OUT3
OUT2 10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HA5024
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Output Current (Note 4) . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating (Note 3) Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (C/W)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . 4.5V to 15V
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175C Maximum Junction Temperature (Plastic Package, Note 1) . . . 150C Maximum Storage Temperature Range . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175C for die, and below 150C for plastic packages. See Application Information section for safe operating area information. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. The non-inverting input of unused amplifiers must be connected to GND. 4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 15mA for maximum reliability.
Electrical Specifications
VSUPPLY = 5V, RF = 1k, AV = +1, RL = 400, CL 10pF,Unless Otherwise Specified (NOTE 11) TEST TEMP. LEVEL (C)
PARAMETER INPUT CHARACTERISTICS Input Offset Voltage (VIO)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
A A
25 Full Full Full 25 Full 25 Full Full 25 Full 25 Full 25 Full 25,85 -40 25,85 -40 25 Full
53 50 60 55 2.5 -
0.8 1.2 5 3 4 10 6 10 -
3 5 3.5 8 20 0.15 0.5 0.1 0.3 12 30 15 30 0.4 1.0
mV mV mV V/C dB dB dB dB V A A A/V A/V A/V A/V A A A A A/V A/V
Delta VIO Between Channels Average Input Offset Voltage Drift VIO Common Mode Rejection Ratio Note 5
A B A A
VIO Power Supply Rejection Ratio
3.5V VS 6.5V
A A
Input Common Mode Range Non-Inverting Input (+IN) Current
Note 5
A A A
+IN Common Mode Rejection 1 (+IBCMR =--------- ) R IN +IN Power Supply Rejection
Note 5
A A
3.5V VS 6.5V
A A
Inverting Input (-IN) Current
A A
Delta -IN BIAS Current Between Channels
A A
-IN Common Mode Rejection
Note 5
A A
2
3550.6 February 8, 2006
HA5024
Electrical Specifications
VSUPPLY = 5V, RF = 1k, AV = +1, RL = 400, CL 10pF,Unless Otherwise Specified (Continued) (NOTE 11) TEST TEMP. LEVEL (C) A A Input Noise Voltage +Input Noise Current -Input Noise Current TRANSFER CHARACTERISTICS Transimpedence Note 16 A A Open Loop DC Voltage Gain RL = 400, VOUT = 2.5V 25A A Open Loop DC Voltage Gain RL = 100, VOUT = 2.5V A A OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150 A A Output Current Output Current, Short Circuit Output Current, Disabled (Note 5) Output Disable Time Output Enable Time Output Capacitance Disabled POWER SUPPLY CHARACTERISTICS Supply Voltage Range Quiescent Supply Current Supply Current, Disabled Disable Pin Input Current Minimum Pin 8 Current to Disable Maximum Pin 8 Current to Enable AC CHARACTERISTICS (AV = +1) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.25% VOUT = 100mV 2V Output Step 2V Output Step Note 8 Note 9 Note 10 Note 10 Note 10 B B B B B B B B B 25 25 25 25 25 25 25 25 25 275 22 350 28 6 6 6 4.5 125 50 75 V/s MHz ns ns ns % MHz ns ns DISABLE = 0V DISABLE = 0V Note 6 Note 7 A A A A A A 25 Full Full Full Full Full 5 350 7.5 5 1.0 15 10 7.5 1.5 20 V mA/Op Amp mA/Op Amp mA A A RL = 150 VIN = 2.5V, VOUT = 0V DISABLE = 0V, VOUT = 2.5V, VIN = 0V Note 12 Note 13 Note 14 B A A B B B 25 Full Full Full Full 25 25 25 2.5 2.5 16.6 40 3.0 3.0 20.0 60 40 40 15 2 V V mA mA A s ns pF 25 Full 25 Full 25 Full 1.0 0.85 70 65 50 45 M M dB dB dB dB f = 1kHz f = 1kHz f = 1kHz B B B 25 Full 25 25 25
PARAMETER -IN Power Supply Rejection
TEST CONDITIONS 3.5V VS 6.5V
MIN -
TYP 4.5 2.5 25.0
MAX 0.2 0.5 -
UNITS A/V A/V nV/Hz pA/Hz pA/Hz
3
3550.6 February 8, 2006
HA5024
Electrical Specifications
VSUPPLY = 5V, RF = 1k, AV = +1, RL = 400, CL 10pF,Unless Otherwise Specified (Continued) (NOTE 11) TEST TEMP. LEVEL (C)
PARAMETER AC CHARACTERISTICS (AV = +2, RF = 681) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.25% Gain Flatness
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Note 8 Note 9 Note 10 Note 10 Note 10
B B B B B B
25 25 25 25 25 25 25 25 25 25 25
-
475 26 6 6 6 12 95 50 100 0.02 0.07
-
V/s MHz ns ns ns % MHz ns ns dB dB
VOUT = 100mV 2V Output Step 2V Output Step 5MHz 20MHz
B B B B B
AC CHARACTERISTICS (AV = +10, RF = 383) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.1% VIDEO CHARACTERISTICS Differential Gain (Note 15) Differential Phase (Note 15) NOTES: 5. VCM = 2.5V. At -40C Product is tested at VCM = 2.25V because short test duration does not allow self heating. 6. RL = 100, VIN = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is considered disabled when -10mV VOUT +10mV. 7. VIN = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA5024 remaining enabled. The HA5024 is considered disabled when the supply current has decreased by at least 0.5mA. 8. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points. Slew Rate 9. FPBW = ---------------------------- ; V = 2V . 2V PEAK PEAK 10. RL = 100, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay. 11. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only. 12. VIN = +2V, DISABLE = +5V to 0V. Measured from the 50% point of DISABLE to VOUT = 0V. 13. VIN = +2V, DISABLE = 0V to +5V. Measured from the 50% point of DISABLE to VOUT = 2V. 14. VIN = 0V, Force VOUT from 0V to 2.5V, tR = tF = 50ns, DISABLE = 0V. 15. Measured with a VM700A video tester using an NTC-7 composite VITS. 16. VOUT = 2.5V. At -40C Product is tested at VOUT = 2.25V because short test duration does not allow self heating. RL = 150 RL = 150 B B 25 25 0.03 0.03 % Degrees VOUT = 100mV 2V Output Step 2V Output Step Note 8 Note 9 Note 10 Note 10 Note 10 B B B B B B B B B 25 25 25 25 25 25 25 25 25 350 28 475 38 8 9 9 1.8 65 75 130 V/s MHz ns ns ns % MHz ns ns
4
3550.6 February 8, 2006
HA5024 Test Circuits and Waveforms
+
DUT
50 HP4195 NETWORK ANALYZER 50
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
(NOTE 17) 100 VIN 50 +
(NOTE 17) 100 DUT VOUT RL 100 VIN 50 RI 681 +
DUT VOUT RL 400
-
-
RF , 681
RF , 1k
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT NOTE:
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT
17. A series input resistor of 100 is recommended to limit input currents in case input signals are present before the HA5024 is powered up.
Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div. FIGURE 4. SMALL SIGNAL RESPONSE
Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div. Horizontal Scale: 50ns/Div. FIGURE 5. LARGE SIGNAL RESPONSE
5
3550.6 February 8, 2006
Schematic
V+
(One Amplifier of Four)
R2 800
R5 2.5K
R6 15K
D2
R10 820
QP8
QP9 QP11
R15 400
R19 400 QP14 R17 280 R18 280
R27 200
R33 2K QP18 QP19
R29 9.5
QP1 QN5
QP5
R11 1K QP10 QN12
R31 5
R24 140 R20 140
QP16 QP20
6
R8 1.25K QN8 QP2 R1 60K QN1 R7 15K QP4 DIS R3 6K QP3 QN6 QP6 R12 280 +IN QN2 QN10 D1 QN4 QN3 QP7 R13 1K QN7 R4 800 VR33 800 R9 820 QN9 QN11
3550.6 February 8, 2006
QP15 C1 1.4pF
QP12 -IN QN13 QP13
R28 20 QP17 QN17 C2 1.4pF QN15 R21 140 QN21 R32 5 QN20 R26 200 QN19 R30 7 OUT R25 20
HA5024
R14 280 QN14 R16 400
R22 280
R25 140 QN16 QN18
R23 400
R26 200
HA5024 Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response, see Figure 11 and Figure 12 in the Typical Performance Curves section, illustrate the performance of the HA5024 in various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn't as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier's unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier's bandwidth is inversely proportional to RF . The HA5024 design is optimized for a 1000 RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth.
GAIN (ACL) -1 +1 +2 +5 +10 -10 RF () 750 1000 681 1000 383 750 BANDWIDTH (MHz) 100 125 95 52 65 22
Driving Capacitive Loads
Capacitive loads will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as shown in Figure 6.
100 VIN RT RF RI + R VOUT CL
-
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION RESISTOR, R
The selection criteria for the isolation resister is highly dependent on the load, but 27 has been determined to be a good starting value.
Power Dissipation Considerations
Due to the high supply current inherent in quad amplifiers, care must be taken to insure that the maximum junction temperature (TJ, see Absolute Maximum Ratings) is not exceeded. Figure 7 shows the maximum ambient temperature versus supply voltage for the available package styles (Plastic DIP, SOIC). At 5VDC quiescent operation both package styles may be operated over the full industrial range of -40C to 85C. It is recommended that thermal calculations, which take into account output power, be performed by the designer.
130 MAX. AMBIENT TEMPERATURE 120 110 100 90 80 70 60 50 5 7 9 11 13 15 SOIC PDIP
PC Board Layout
The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. If leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. Attention must be given to decoupling the power supplies. A large value (10F) tantalum or electrolytic capacitor in parallel with a small value (0.1F) chip capacitor works well in most cases. A ground plane is strongly recommended to control noise. Care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. It is recommended that the ground plane be removed under traces connected to -IN, and that connections to -IN be kept as short as possible to minimize the capacitance from this node to ground. 7
SUPPLY VOLTAGE (V)
FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE vs SUPPLY VOLTAGE
Enable/Disable Function
When enabled the amplifier functions as a normal current feedback amplifier with all of the data in the electrical specifications table being valid and applicable. When disabled the amplifier output assumes a true high impedance state and the supply current is reduced significantly.
3550.6 February 8, 2006
HA5024
The circuit shown in Figure 8 is a simplified schematic of the enable/disable function. The large value resistors in series with the DISABLE pin makes it appear as a current source to the driver. When the driver pulls this pin low current flows out of the pin and into the driver. This current, which may be as large as 350A when external circuit and process variables are at their extremes, is required to insure that point "A" achieves the proper potential to disable the output.The driver must have the compliance and capability of sinking all of this current. When VCC is +5V the DISABLE pin may be driven with a dedicated TTL gate. The maximum low level output voltage of the TTL gate, 0.4V, has enough compliance to insure that the amplifier will always be disabled even though D1 will not turn on, and the TTL gate will sink enough current to keep point "A" at its proper voltage. When VCC is greater than +5V the DISABLE pin should be driven with an open collector device that has a breakdown rating greater than VCC . Referring to Figure 8, it can be seen that R6 will act as a pull-up resistor to +VCC if the DISABLE pin is left open. In those cases where the enable/disable function is not required on all circuits some circuits can be permanently enabled by letting the DISABLE pin float. If a driver is used to set the enable/disable level, be sure that the driver does not sink more than 20A when the DISABLE pin is at a high level. TTL gates, especially CMOS versions, do not violate this criteria so it is permissible to control the enable/disable function with TTL.
+VCC R6 15K D1 R7 15K ENABLE/DISABLE INPUT R8 QP3 R10 R33 QP18 A R6 75 R8 681 VIDEO INPUT #3 R11 75 R13 681 VIDEO INPUT #4 R16 75 R18 681 (NOTE 17) 100 18 19 U1D
When the plus supply rail is 5V the disable pin can be driven by a dedicated TTL gate as discussed earlier. If a multiplexer IC or its equivalent is used to select channels its logic must be break before make. When these conditions are satisfied the HA5024IP is often used as a remote video multiplexer, and the multiplexer may be extended by adding more amplifier ICs.
Low Impedance Multiplexer
Two common problems surface when you try to multiplex multiple high speed signals into a low impedance source such as an A/D converter. The first problem is the low source impedance which tends to make amplifiers oscillate and causes gain errors. The second problem is the multiplexer which supplies no gain, introduces all kinds of distortion and limits the frequency response. Using op amps which have an enable/disable function, such as the HA5024, eliminates the multiplexer problems because the external mux chip is not needed, and the HA5024 can drive low impedance (large capacitance) loads if a series isolation resistor is used.
VIDEO INPUT #1 R1 75 (NOTE 17) 100 3 + 2U1A R3 681 (NOTE 17) 100 4 R2 681 R5 2000 1 R21 100 +5V 2 3 4 R10 2000 S1 ALL OFF 1 R4 75 VIDEO OUTPUT TO 75 LOAD
U1B
8 + 97 R7 681
10
R9 75
-5V (NOTE 17) 100 13 15 11 12 +
R14 75
-
U1C
14 R12 681 +5V 6 + 20 R19 75 R15 2000
FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE FUNCTION
Typical Applications
Four Channel Video Multiplexer
Referring to the amplifier U1A in Figure 9, R1 terminates the cable in its characteristic impedance of 75, and R4 back terminates the cable in its characteristic impedance. The amplifier is set up in a gain configuration of +2 to yield an overall network gain of +1 when driving a double terminated cable. The value of R3 can be changed if a different network gain is desired. R5 holds the disable pin at ground thus inhibiting the amplifier until the switch, S1, is thrown to position 1. At position 1 the switch pulls the disable pin up to the plus supply rail thereby enabling the amplifier. Since all of the actual signal switching takes place within the amplifier, its differential gain and phase parameters, which are 0.03% and 0.03 degrees respectively, determine the circuit's performance. The other three circuits, U1B through U1D, operate in a similar manner. 8
-
17 R17 681 R20 2000
+5V IN 0.1F
+5V -5V IN 10F 0.1F
-5V 10F
NOTES: 18. U1 is HA5024IP. 19. All resistors in . 20. S1 is break before make. 21. Use ground plane. FIGURE 9. FOUR CHANNEL VIDEO MULTIPLEXER
3550.6 February 8, 2006
HA5024
Referring to Figure 10, both inputs are terminated in their characteristic impedance; 75 is typical for video applications. Since the drivers usually are terminated in their characteristic impedance the input gain is 0.5, thus the amplifiers, U2, are configured in a gain of +2 to set the circuit gain equal to one. Resistors R2 and R3 determine the amplifier gain, and if a different gain is desired R2 should be changed according to the equation G = (1 + R3/R2). R3 sets the frequency response of the amplifier so you should refer to the manufacturers data sheet before changing its value. R5, C1 and D1 are an asymmetrical charge/discharge time circuit which configures U1 as a break before make switch to prevent both amplifiers from being active simultaneously. If this design is extended to more channels the drive logic must be designed to be break before make. R4 is enclosed in the feedback loop of the amplifier so that the large open loop amplifier gain of U2 will present the load with a small closed loop output impedance while keeping the amplifier stable for all values of load capacitance. The circuit shown in Figure 10 was tested for the full range of capacitor values with no oscillations being observed; thus, problem one has been solved.The frequency and gain characteristics of the circuit are now those of the amplifier independent of any multiplexing action; thus, problem two has been solved. The multiplexer transition time is approximately 15s with the component values shown.
INPUT B R1A 75 INPUT A R1B 75 D1A 1N4148 R5A U1C 2000 C1A 0.047F CHANNEL SWITCH
R3A 681 R4A U2A 27 16 1+ 4 -5V 2 100 3 (NOTE 17) 0.01F R1A 681
R3B 681 R2B 681 R4B 27 OUTPUT +5V
R5B 2000 INHIBIT U1A R6 100K U1B U1D
100 (NOTE 17)
7 U2B - 10 6 + 13 5
0.01F
D1B 1N4148
C1B 0.047F
NOTES: 22. U2: HA5022/24. 23. U1: CD4011.
FIGURE 10. LOW IMPEDANCE MULTIPLEXER
9
3550.6 February 8, 2006
HA5024 Typical Performance Curves
5 4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 2 10 FREQUENCY (MHz) 100 200 AV = 10, RF = 383 VOUT = 0.2VP-P CL = 10pF AV = 2, RF = 681 AV = 5, RF = 1k NORMALIZED GAIN (dB) AV = +1, RF = 1k
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified
5 4 3 2 1 0 -1 -2 -3 AV = -5 -4 -5 2 10 FREQUENCY (MHz) 100 200 AV = -10 VOUT = 0.2VP-P CL = 10pF RF = 750 AV = -1
AV = -2
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE
-3dB BANDWIDTH (MHz)
FIGURE 12. INVERTING FREQUENCY RESPONSE
140 VOUT = 0.2VP-P CL = 10pF AV = +1
NONINVERTING PHASE (DEGREES)
-45 -90 -135 -100 -225 -270 -315 -360 2 VOUT = 0.2VP-P CL = 10pF 10 FREQUENCY (MHz) 100 AV = -10, RF = 750 AV = -1, RF = 750 AV = +10, RF = 383
135 90 45 0 -45 -90 -135 -180 200
INVERTING PHASE (DEGREES)
0
AV = +1, RF = 1k
180
130
5 GAIN PEAKING 500 700 900 1100 1300 FEEDBACK RESISTOR () 0 1500
FIGURE 13. PHASE RESPONSE AS A FUNCTION OF FREQUENCY
100 VOUT = 0.2VP-P CL = 10pF AV = +2 95
FIGURE 14. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE
-3dB BANDWIDTH (MHz)
-3dB BANDWIDTH (MHz)
130
120
-3dB BANDWIDTH
-3dB BANDWIDTH 90 10 GAIN PEAKING (dB)
110
6 GAIN PEAKING (dB)
100
GAIN PEAKING VOUT = 0.2VP-P CL = 10pF AV = +1
4
5 GAIN PEAKING 350 500 650 800 950 0 1100
90
2
80 0 200 400 600 800 LOAD RESISTOR ()
0 1000
FEEDBACK RESISTOR ()
FIGURE 15. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE
FIGURE 16. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE
10
3550.6 February 8, 2006
GAIN PEAKING (dB)
120
-3dB BANDWIDTH
10
HA5024 Typical Performance Curves
80 VOUT = 0.2VP-P CL = 10pF AV = +10 -3dB BANDWIDTH (MHz) 60 OVERSHOOT (%) 12
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified (Continued)
16 VOUT = 0.1VP-P CL = 10pF VSUPPLY = 5V, AV = +2
40
6
VSUPPLY = 15V, AV = +2 VSUPPLY = 5V, AV = +1 VSUPPLY = 15V, AV = +1
20
0 200 350 500 650 FEEDBACK RESISTOR () 800 950
0 0 200 400 600 LOAD RESISTANCE () 800 1000
FIGURE 17. BANDWIDTH vs FEEDBACK RESISTANCE
FIGURE 18. SMALL SIGNAL OVERSHOOT vs LOAD RESISTANCE
0.08
0.10 FREQUENCY = 3.58MHz 0.08 DIFFERENTIAL GAIN (%) RL = 75 DIFFERENTIAL PHASE (DEGREES)
FREQUENCY = 3.58MHz
0.06
0.06
0.04 RL = 150 RL = 75
0.04
RL = 150
0.02 RL = 1k 0.00
0.02 RL = 1k 0.00 3 5 7 9 11 SUPPLY VOLTAGE (V) 13 15
3
5
7 9 11 SUPPLY VOLTAGE (V)
13
15
FIGURE 19. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE
-40 VOUT = 2.0VP-P CL = 30pF -50
FIGURE 20. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
0 -10 REJECTION RATIO (dB) HD2 -20 -30 -40 -50 -60 -70 HD3 -80 10 0.001
AV = +1
DISTORTION (dBc)
-60 3RD ORDER IMD -70 HD2
CMRR
HD3
-80
NEGATIVE PSRR POSITIVE PSRR 0.01 0.1 FREQUENCY (MHz) 1 10 30
-90 0.3
1 FREQUENCY (MHz)
FIGURE 21. DISTORTION vs FREQUENCY
FIGURE 22. REJECTION RATIOS vs FREQUENCY
11
3550.6 February 8, 2006
HA5024 Typical Performance Curves
8.0 RL = 100 VOUT = 1.0VP-P AV = +1 7.5
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified (Continued)
12 RLOAD = 100 VOUT = 1.0VP-P PROPAGATION DELAY (ns) 10 AV = +10, RF = 383
PROPAGATION DELAY (ns)
7.0
8 AV = +2, RF = 681 6 AV = +1, RF = 1k
6.5
6.0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
4 3 5 7 9 11 SUPPLY VOLTAGE (V) 13 15
FIGURE 23. PROPAGATION DELAY vs TEMPERATURE
FIGURE 24. PROPAGATION DELAY vs SUPPLY VOLTAGE
500 VOUT = 2VP-P 450 NORMALIZED GAIN (dB) 400 SLEW RATE (V/s) 350 300 250 200 150 100 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 - SLEW RATE + SLEW RATE
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 AV = +1, RF = 1k -0.8 -1.0 -1.2 5 10 15 20 FREQUENCY (MHz) 25 30 AV = +10, RF = 383 AV= +5, RF = 1k AV= +2, RF = 681 VOUT = 0.2VP-P CL = 10pF
FIGURE 25. SLEW RATE vs TEMPERATURE
FIGURE 26. NON-INVERTING GAIN FLATNESS vs FREQUENCY
100 AV = +10, RF = 383 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz) 80 -INPUT NOISE CURRENT 800 1000
0.8 0.6 0.4 NORMALIZED GAIN (dB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 5 10 15 20 25 30 FREQUENCY (MHz) AV = -10 AV = -2 AV = -5 AV = -1 VOUT = 0.2VP-P CL = 10pF RF = 750
60 +INPUT NOISE CURRENT 40 INPUT NOISE VOLTAGE 20
600
400
200
0 0.01
0.1
1 FREQUENCY (kHz)
10
0 100
FIGURE 28. INPUT NOISE CHARACTERISTICS FIGURE 27. INVERTING GAIN FLATNESS vs FREQUENCY
12
3550.6 February 8, 2006
HA5024 Typical Performance Curves
1.5
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified (Continued)
2
1.0 VIO (mV)
BIAS CURRENT (A)
0
0.5
-2
0.0 -60
-4 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) TEMPERATURE (C)
FIGURE 29. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 30. +INPUT BIAS CURRENT vs TEMPERATURE
4000 22
TRANSIMPEDANCE (k)
BIAS CURRENT (A)
20
3000
2000
18
16 -60
-40
-20
0
20
40
60
80
100
120
140
1000 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 31. -INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 32. TRANSIMPEDANCE vs TEMPERATURE
25
74 72 REJECTION RATIO (dB) +PSRR
20 125C ICC (mA) 15
55C
70 68 -PSRR 66 64 62 60 58 -100 CMRR
10 25C 5 3 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V)
-50
0
50
100
150
200
250
TEMPERATURE (C)
FIGURE 33. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 34. REJECTION RATIO vs TEMPERATURE
13
3550.6 February 8, 2006
HA5024 Typical Performance Curves
40
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified (Continued)
4.0
SUPPLY CURRENT (mA)
20
OUTPUT SWING (V) 3 4 5 6 7 8 9 10 11 12 13 14 15
30
+5V
+10V
+15V
3.8
10
0 0 1 2 DISABLE INPUT VOLTAGE (V)
3.6 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
FIGURE 35. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE
FIGURE 36. OUTPUT SWING vs TEMPERATURE
30 VS = 15V
1.2
1.1 VOUT (VP-P) 20 VS = 10V VIO (mV) 10.00
1.0
10 VS = 4.5V 0.9
0 0.01
0.8 0.10 1.00 -60 -40 -20 0 20 40 60 80 100 120 140 LOAD RESISTANCE (k) TEMPERATURE (C)
FIGURE 37. OUTPUT SWING vs LOAD RESISTANCE
FIGURE 38. INPUT OFFSET VOLTAGE CHANGE BETWEEN CHANNELS vs TEMPERATURE
1.5
30
BIAS CURRENT (A)
25 1.0 ICC (mA) 20 25C
-55C
15
0.5 10 125C
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
5 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) 13 14 15
FIGURE 39. INPUT BIAS CURRENT CHANGE BETWEEN CHANNELS vs TEMPERATURE
FIGURE 40. DISABLE SUPPLY CURRENT vs SUPPLY VOLTAGE
14
3550.6 February 8, 2006
HA5024 Typical Performance Curves
-30 AV = +1 VOUT = 2VP-P -40 SEPARATION (dB) ENABLE TIME (ns)
VSUPPLY = 5V, AV = +1, RF = 1k, RL = 400, TA = 25C, Unless Otherwise Specified (Continued)
32 30 28 26 24 22 20 18 16 14 DISABLE -0.5 0 0.5 1.0 1.5 2.0 DISABLE ENABLE ENABLE 20 18 16 14 12 10 8 6 4 2 0 2.5 DISABLE TIME (s) PHASE ANGLE (DEGREES)
-50
-60
-70
-80 0.1
1 FREQUENCY (MHz)
10
30
12 -2.5 -2.0 -1.5 -1.0
OUTPUT VOLTAGE (V)
FIGURE 41. CHANNEL SEPARATION vs FREQUENCY
FIGURE 42. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
0 -10 FEEDTHROUGH (dB) -20 -30 -40 -50 -60 -70 -80 0.1
DISABLE = 0V VIN = 5VP-P RF = 750
TRANSIMPEDANCE (M)
10 1 0.1 0.01 0.001 180 135 90 45 0 -45 -90 RL = 100
1 FREQUENCY (MHz)
10
20
0.001
0.01
0.1 1 FREQUENCY (MHz)
10
-135 100
FIGURE 43. DISABLE FEEDTHROUGH vs FREQUENCY
FIGURE 44. TRANSIMPEDANCE vs FREQUENCY
TRANSIMPEDANCE (M)
10 1 0.1 PHASE ANGLE (DEGREES) 0.01 0.001 180 135 90 45 0 -45 -90 -135 0.001 0.01 0.1 1 10 100 FREQUENCY (MHz) RL = 400
FIGURE 45. TRANSIMPEDENCE vs FREQUENCY
15
3550.6 February 8, 2006
HA5024 Die Characteristics
DIE DIMENSIONS: 2680m x 2600m x 483m METALLIZATION: Type: Metal 1: AlCu (1%) Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AlCu (1%) Thickness: Metal 2: 16kA 0.8kA SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 248 PROCESS: High Frequency Bipolar Dielectric Isolation PASSIVATION: Type: Nitride Thickness: 4kA 0.4kA
Metallization Mask Layout
HA5024
-IN1 OUT1 OUT4 -IN4
2 +IN1 3
1
20
19 18 +IN4
DIS1
4
17
DIS4
V+
6
15
V-
DIS2
7
14
DIS3
+IN2
8 9 10 11 12
13
+IN3
-IN2
OUT2
OUT3
-IN3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
3550.6 February 8, 2006

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